Differential readout from pixels in CMOS sensor

ABSTRACT

The present invention provides an improved pixel readout circuit that compensates for common mode noise during a read out operation. This is accomplished by using a differential readout of the signal and reset value from the desired pixel compared with the reset value from a reference pixel. In this manner common mode noise can be offset and therefore minimized. In one embodiment of the invention, the reference pixel is the nearest neighbor pixel in the same row. In another embodiment, the reference pixel is the nearest neighboring pixel in a different row.

FIELD OF THE INVENTION

The invention relates generally to improved semiconductor imagingdevices and in particular to an imaging device which can be fabricatedusing a standard CMOS process. Particularly, the invention relates to aCMOS imager having an array of image sensing cells and to the drivingsignals which operate the cells.

BACKGROUND OF THE INVENTION

There is a current interest in CMOS active pixel imagers for possibleuse as low cost imaging devices. An exemplary pixel circuit of a CMOSactive pixel sensor (APS) is described below with reference to FIG. 1.Active pixel sensors can have one or more active transistors within thepixel unit cell, can be made compatible with CMOS technologies andpromise higher readout rates compared to passive pixel sensors. The FIG.1 exemplary pixel cell 10 is a 4T APS, where the 4T is commonly used inthe art to designate use of four transistors to operate the pixel. A 4Tpixel has a photodiode 162, a reset transistor 184, a transfertransistor 182, a source follower transistor 186, and a row selecttransistor 188. It should be understood that while FIG. 1 shows thecircuitry for operation of a single pixel, and that in practical usethere will be an M times N array of pixels arranged in rows and columnswith the pixels of the array accessed using row and column selectcircuitry, as described in more detail below.

The pixel cell 150 includes the photodiode 162 which converts incidentphotons to electrons. The electrons are passed to a collection node A bytransfer transistor 182. A source follower transistor 186 has its gateconnected to node A and thus amplifies the signal appearing at Node A.When a particular row containing cell 150 is selected by a row selectiontransistor 188, the signal amplified by transistor 186 is passed on acolumn line 170 to the readout circuitry. The photodiode 162 accumulatesa photo-generated charge in a doped region of the substrate. It shouldbe understood that the CMOS imager may include a photogate or otherphoton to charge converting device, in lieu of a photodiode, as theinitial accumulator for photo-generated charge.

The gate of transfer transistor 182 is coupled to a transfer controlsignal (tx) line 180, thereby serving to control the coupling of thephotodiode 162 to the node A. A reset voltage source Vrst is coupled byconductive line 163 through reset transistor 184 to node A. The gate ofreset transistor 184 is coupled to a reset control line rst 190 whichserves to control the reset operation in which Vrst is connected to nodeA. The row select control line 160 is coupled to all of the pixels ofthe same row of the array. Voltage source Vdd is coupled to column line170 by conductive line 165 through transistors 186 and 188. Although notshown in FIG. 1, column line 170 is coupled to all of the pixels of thesame column of the array and typically has a current sink at its lowerend. The gate of row select transistor 188 is coupled to row selectcontrol line 160. The Vrst power supply is typically connected to theVdd power supply, so that the Vrst voltage is equivalent to Vdd (e.g.,Vdd_pix).

As know in the art, a value is read from pixel 150 in a two stepprocess. First, node A is reset by turning on reset transistor 184 andthe reset voltage (e.g., Vrst) is read out to column line 170 by thesource follower transistor 186 through the activated row selecttransistor 188. Second, after pixel reset, a charge integration periodoccurs during which the photodiode 162 converts photons to electrons.After the integration period, transfer transistor 182 turns on and theintegrated charge is passed by transfer transistor from the photodiode162 to node A, where it is amplified by source follower transistor 186and passed to column line 170 by row access transistor 188. As a result,the two different values—the reset voltage and the signal voltage—arereadout from the pixel and sent by the column line 170 to the readoutcircuitry where each is sampled and held for further processing as knownin the art.

All pixels in a row are read out simultaneously onto respective columnlines 170 and the column lines are activated in sequence for pixel resetand signal voltage read out. The rows of pixels are read out in sequenceonto the respective column lines.

FIG. 2 shows an exemplary CMOS active pixel sensor integrated circuitchip that includes an array of active pixel sensors 230 and a controller232 which provides timing and control signals to enable reading out ofsignals stored in the pixels in a manner commonly known to those skilledin the art. Exemplary arrays have dimensions of M times N pixels, withthe size of the array 230 depending on a particular application. Theimager is read out a row at a time using a column parallel readoutarchitecture. The controller 232 selects a particular row of pixels inthe array 230 by controlling the operation of row addressing circuit 234and row drivers 240. Charge signals stored in the selected row of pixelsare provided on the column lines 170 to a readout circuit 242 in themanner described above. The pixel signal read from each of the columnsthen can be read out sequentially using a column addressing circuit 244.Differential pixel signals (Vrst, Vsig) corresponding to the read outreset signal and integrated charge signal are provided as respectiveoutputs Vout1, Vout2 of the readout circuit 242.

FIG. 3 more closely shows the rows and columns 349 of CMOS active pixelsensors 350. Each column includes multiple rows of sensors 350. Signalsfrom the active pixel sensors 350 in a particular column can be read outto a readout circuit 352 associated with that column. The read outcircuit 352 includes sample and hold circuitry for acquiring the pixelreset and integrated charge signals. Signals stored in the readoutcircuits 352 then can be read sequentially column-by-column to an outputstage 354 which is common to the entire array of pixels 330. The analogoutput signals can then be sent, for example, to a differential analogcircuit and which subtracts the reset and integrated charge signals andsends them to an analog-to-digital converter (ADC) or the reset andintegrated charge signals are each supplied to the analog-to-digitalconverter.

As fabrication techniques get better an increasing number of digitalprocessing circuits are being implemented on the same chip as an imagesensor. This increases substrate noise coupling to a pixel, which cancompromise the signal to noise ratio of the image sensor core. Thesubstrate noise occurs when spurious noise signals are injected locallyinto the substrate through ohmic or capacitive coupling, therebybreaking the equipotentiality of the substrate.

Accordingly, when the reset signal and the integrated charge signal areread out at different times, the potential of the local ground may notbe the same. The sensing node A (FIG. 1) of each pixel is capacitivelycoupled to a local ground and is dynamically affected by local substratenoise. The common mode noise, including ground noise, during the resetphase is Vcm1 and during the signal phase is Vcm2. If Vsig is the signalvoltage and Vrst is the reset voltage, then the differential voltageVdiff=(Vsig+Vcm2)−(Vrst+Vcm1). Since Vcm2 does not equal Vcm1, they donot cancel out in the differential signal, and instead adversely affectthe pixel signal ultimately produced.

One way of dealing with substrate noise is to use a dummy circuit,similar to a pixel circuit, and located near the pixel circuit, butshielded from light as a reference signal source. Theoretically, thepixel and dummy circuit would see the same substrate voltage which canthen be correlated in processing. But this will cause a decreased fillfactor for the pixels, and for some architectures will cause an increasein KTC (thermal) noise.

It would be desirable to have a pixel readout circuit that compensatesfor substrate and other common mode noise that is encountered during apixel read out operation.

BRIEF SUMMARY OF THE INVENTION

The present invention provides an improved pixel readout circuit andmethod of operation which minimizes substrate and other common modenoise during a read out operation. The circuit improves the consistencyof the pixel to pixel output of the pixel array and increases thedynamic range of the pixel output. This is accomplished by obtaining adifferential readout of the reset signal and integrated charge signalfrom a desired pixel along with a reset signal and a comparison signalfrom a different reference pixel, where the comparison signal is a resetsignal taken in the reference pixel at the same time that the chargeaccumulated signal is taken in the desired pixel. Thus, a reset value istaken twice from the reference pixel; once during reset sampling phase,e.g., the reset value, and once during signal sampling phase e.g., thecomparison value,. In this manner common mode noise can be minimized bya combination of signals from the desired and reference pixels. In oneexemplary embodiment of the invention, the reference pixel is thenearest neighbor pixel in the same row. In another exemplary embodiment,the reference pixel is the nearest neighboring pixel in a different rowof the same column.

Since any given pixel of the array serves as a desired pixel at one timeand a reference pixel at another time there is no need to fabricateadditional pixels to be used as reference pixels.

These and other features and advantages of the invention will be morereadily understood from the following detailed description of theinvention which is provided in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a prior art active pixel;

FIG. 2 is a block diagram of a prior art CMOS active sensor chip;

FIG. 3 is a block diagram of a prior art array of active pixels and anassociated readout circuit;

FIG. 4 is a sample and hold circuit in accordance with an exemplaryembodiment of the invention;

FIG. 5 is a differential readout pixel circuit in accordance with anexemplary embodiment of the invention;

FIG. 6 is a simplified timing diagram associated with the circuitry ofFIG. 5;

FIG. 7 is a differential readout pixel circuit in accordance with ananother exemplary embodiment of the invention;

FIG. 8 is a simplified timing diagram associated with the circuitry ofFIG. 7;

FIG. 9 is a differential readout pixel circuit in accordance with ananother exemplary embodiment of the invention;

FIG. 10 is a simplified timing diagram associated with the circuitry ofFIG. 9;

FIG. 11 is a block diagram representation of a processor-based systemincorporating a CMOS imaging device in accordance with an exemplaryembodiment of the invention; and

FIG. 12 is an exemplary embodiment of a pixel array having shareddiffusion nodes.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. These embodiments are described in sufficient detail toenable those of ordinary skill in the art to make and use the invention,and it is to be understood that structural, logical or proceduralchanges may be made to the specific embodiments disclosed withoutdeparting from the spirit and scope of the present invention.

To minimize common ground noise and the loss of fill factor the presentinvention utilizes a neighbor pixel as the source of a referencedifferential signal which is combined with the output of a desiredpixel. In an exemplary embodiment, the actual photosignal from theneighboring pixel is not read when the neighboring pixel acts asreference pixel, only a reference value is taken as a comparison signalfrom the reference pixel at the time of taking the photo signal from thedesired pixel. A reset signal is also taken from the reference pixel atthe time of taking the reset signal of the desired pixel. Sinceneighboring pixels share the same local substrate, their ground voltageis substantially identical, and any induced ground noise is alsosubstantially the same. By subtracting the reference values of theneighboring pixel from signals taken from the desired pixel, the groundnoise is cancelled out and therefore removed. The neighboring referencepixel is close to the desired pixel but need not be an adjacent pixel,though use of an adjacent pixel as the reference pixel is desirable tohelp ensure that the desired pixel and reference pixel experience thesame substrate noise effects. Accordingly, the exemplary embodiments ofthe invention described herein utilize an adjacent row pixel as areference pixel and an adjacent column pixel as a reference pixel.

FIG. 4 illustrates sample and hold circuit in accordance with a firstexemplary embodiment of the invention which uses an adjacent row pixelas a reference. In this embodiment, the sample and hold circuit 35 iscapable of sampling and holding two sets of signals simultaneously,e.g., a reset signal and a photo signal from a desired pixel and a resetsignal and a comparison signal and a reference pixel in adjacentcolumns, and then subsequently combining the two sets of signals. Forexample, a reset signal of a desired pixel on column line 402 would bestored on capacitor 418 and the charge accumulated photo signal would bestored on capacitor 420. And similarly, a reset signal for a referencepixel associated with adjacent column line 404 would be stored oncapacitor 414 and a comparison signal would be stored on capacitor 416.A downstream circuit subsequently combines these signals and outputs acharge accumulated signal free of noise.

The circuit 35 is precharged when a pulse Vclamp is applied to switches441, 442, 443, and 444 thereby temporarily coupling Vclamp to thecapacitors 414, 416, 418, 420 thereby placing a Vclamp charge on them.To store the charge accumulated signal of the desired pixel on capacitor420, a pulse signal is enabled which closes the SHS switch 412 andcouples the desired pixel with the capacitor 420 through the column line402 and then the SHS switch 412 is opened, which retains the chargeaccumulated signal in the capacitor 420 (assuming that Col. Selectswitch 428 is open). Similarly, to store the reset signal of the desiredpixel on capacitor 418, a pulse signal is enabled which closes the SHRswitch 410 and couples the desired pixel with the capacitor 418 throughthe column line 402 and then the SHR switch 410 is opened, which retainsthe signal in the capacitor 418 (assuming that Col. Select switch 426 isopen). Storing the reset and comparison signals of the reference pixelis done in an analogous manner. A pulse signal is enabled which closesthe SHS switch 408 and couples the reference pixel with the capacitor416 through the column line 404 and then the SHS switch 408 is opened,which retains the comparison signal in the capacitor 416 (assuming thatCol. Select switch 424 is open). Similarly, to store the reset signal ofthe reference pixel on capacitor 414, a pulse signal is enabled whichcloses the SHR switch 406 and couples the reference pixel with thecapacitor 414 through the column line 404 and then the SHR switch 406 isopened, which retains the signal in the capacitor 414 (assuming thatCol. Select switch 422 is open).

In order to read out the stored reset, charge accumulated, andcomparison signals of the desired and reference pixels from thecapacitors 414, 416, 418, and 420 a pulse signal is enabled closing CBswitches 448, 449 and Col. Select switches 422, 424, 426, and 428 andthereby coupling capacitors 414, 416 with differential amplifier 432 andcapacitors 418, 420 with differential amplifier 434. Signals output fromamplifiers 432 and 434 are coupled to a combining circuit 430 whichcombines these signals and outputs the resulting differential signals.

FIG. 5 illustrates a desired and a reference pixel in accordance withthe first exemplary embodiment of the invention. Assuming pixel 450 isthe desired pixel-the pixel being read from-pixel 452 is the referencepixel located in the neighboring column of the same row. The significantdifference between the circuit in FIG. 1 and the circuit in FIG. 5 isthat an additional transfer gate control line 481 is provided. A pixelserving as a reference pixel is not a dummy pixel and serves as adesired pixel at a different time. Correspondingly, a pixel serving as adesired pixel at one time serves as a reference pixel at a differenttime. The control line 480 and the additional control line 481 arealternately coupled to the pixels in a row (e.g., control line 480 iscoupled to all the pixels in the odd columns of the row and control line481 is coupled to all the pixels in the even columns of the row) whichallows control of the transfer gate transistor in the odd columnsseparate from the control of the transfer gate transistor in the evencolumns.

As indicated above, the common mode noise, including ground noise,during the reset phase for SHR, is Vcm1 and during the signal phase forSHS, is Vcm2. Therefore, if Vsig(n) is the signal voltage of column(n)and Vrst(n) is the reset voltage of column(n), then:

Vdiff(n)=(Vsig(n)+Vcm2)−(Vrst(n)+Vcm1)   (1)

Similarly, if Vsig(n+1) is the signal voltage of column(n+1) andVrst(n+1) is the reset voltage of column(n+1), then:

Vdiff(n+1)=(Vsig(n+1)+Vcm2)−(Vrst(n+1)+Vcm1)   (2)

Using a differential readout circuit, in a manner commonly known in theart, and combining signals of the desired pixel and the reference pixelprovides:

Vsig_diff(n)=((Vsig(n)+Vcm2)−(Vrst(n)+Vcm1))−((Vsig(n+1)+Vcm2)−(Vrst(n+1)+Vcm1))  (3)

However, if during the SHS phase of the reference pixel the transfercontrol gate is not enabled, therefore not permitting the charge on thephotodiode to be coupled to the column line, then Vsig(n+1)=Vrst(n+1),e.g., the comparison signal value of the reference pixel is equivalentto the reset signal value of the reference pixel. Using the differentialreadout circuit described above for combining signals from the desiredpixel and the reference pixel without enabling the transfer control gateduring the SHS phase of the reference pixel removes common mode noise.That is,

$\begin{matrix}\begin{matrix}{{{Vsig\_ diff}(n)} = {\left( {\left( {{{Vsig}(n)} + {{Vcm}\; 2}} \right) - \left( {{{Vrst}(n)} + {{Vcm}\; 1}} \right)} \right) -}} \\{\left( {\left( {{{Vrst}\left( {n + 1} \right)} + {{Vcm}\; 2}} \right) - \left( {{{Vrst}\left( {n + 1} \right)} + {{Vcm}\; 1}} \right)} \right)} \\{= {{{Vsig}(n)} - {{Vrst}(n)}}}\end{matrix} & (4)\end{matrix}$

for the desired pixel. In this manner, the Vsig and the Vrst of thedesired pixel can be offset by the Vrst of the reference pixel tominimize noise while still providing the differential of the reset pixelsignal Vrst(n) and photo signal Vsig(n) of the desired pixel.

The operation of circuits of FIGS. 4 and 5 is now described withreference to the simplified signal timing diagram of FIG. 6. To readfrom desired pixel 450 the rst line 490 is enabled by a reset pulseafter which it is disabled. Node A of desired pixel is reset by thereset voltage Vrst which is read out on line 402 by the SHR pulseapplied to the row select transistor 488 and to the SHR switch of thereadout circuit (Switch 410, FIG. 4). The reset voltage is sampled by asample and hold circuit (FIG. 4) connected to the column line 402. Thus,Vrst of the desired pixel is sampled and stored on capacitor 418. Afterthe reset voltage is stored, and after a charge integration period, thetx1 line 480 is enabled by a transfer pulse. The SHS switch of thereadout circuit (switch 412, FIG. 4) is pulsed thereby storing anintegrated charge pixel signal on capacitor 420. The reference pixel 452is simultaneously read out. The steps to read out the reference pixelare similar with the exception that the transfer gate tx2 line 481 isnot enabled, therefore isolating photo diode 162 and not transferringits charge to Node A. Thus, capacitor 414 connected to the referencepixel stores the reset signal of the reference pixel at the same timethat the desired pixel stores the reset signal on capacitor 418 andcapacitor 416 connected to the reference pixel stores the comparisonsignal of the reference pixel at the same time that the desired pixelstores the integrated charge signal on capacitor 420. The voltagesstored in the sample and hold circuits for the odd and even columns arenow available for the differential readout circuit to determine theVsig_diff(n) in accordance with equation 4.

At a different time, pixel 452 is the desired pixel reading out the oddcolumn pixel 452 and array operation is analogous to reading out evencolumn pixel 450 with the difference that the transfer control line tx2481 corresponding to pixel 452, tx2 line 481, would be enabled insteadof the transfer control line tx1 480. The remaining signals in the FIG.6 timing diagram describe the read out from pixel 452 as a desired pixeland pixel 450 as a reference pixel. Furthermore, when pixel 452 is thedesired pixel, the reference pixel may be pixel 450 or it may bedifferent pixel in the same row, but different column set (e.g., odd oreven) than the desired pixel. Although FIG. 5 only discloses one oddcolumn pixel 450 and even odd pixel 452, all the odd column pixels, andall the even column pixels, in the same row would be read out in thesame manner. Other pixel array rows above and below the row containingpixels 450, 452 would also be read in the similar manner.

Turning to FIG. 7, a differential readout pixel circuit in accordancewith an another exemplary embodiment of the invention is depicted. TheFIG. 7 differential readout pixel circuit 60 differs from thedifferential readout pixel circuit 40 in FIG. 5 in that desired pixel iscompared with a nearest neighbor in the same column, but in the nextrow, either in the row above or row below the row containing the desiredpixel. Additionally, each column of pixels has two associated columnlines with rows of pixels being alternately by row coupled to the columnlines. As seen in FIG. 7, two column lines 670, 671 are used whichpermits read out of both pixels 650, 652 contemporaneously. Thus, pixel650 is read out through column line 670 and pixel 652 is read outthrough column line 671. To effectuate a readout from pixels 650, 652,two different sets of respective controls lines are used: pixel 650,located in column n, has an associated transfer control line(n) 680,reset line(n) 690, and a row select line(n) 660. Pixel 652, located inadjacent column n+1, has an associated transfer control line(n+1) 681,reset line(n+1) 691, and a row select line(n+1) 661. A column sample andhold circuit is required for each of the column lines 678, 671 forstoring both reset values and pixel charge integrated values of thedesired pixel 650 and reference pixel 652.

The operation of circuit of FIG. 7 is now described with reference tothe simplified timing diagram for signal of FIG. 8. To read from desiredpixel 650 and the reference pixel 652, the reset control lines 690, 691are enabled by pulse signals Rstn, Rstn1 (FIG. 8). Then the SHR switchesin the sample and hold circuits for both columns Rstn1 are enabled bysignals SHR_A and SHR_B, thereby storing the reset voltages Vrst(n) andVrst(n+1) for pixels 650, 652. The tx_n line 680 is then pulsed and theSHS switches in the sample and hold circuits are pulsed thereby storingpixel 650, 652 signals Vsig(n) and Vsig(n+1), where Vsig(n) is thecharge integrated signal of the desired pixel 650 and Vsig(n+1) is thecomparison signal of the reference pixel 652 and is equivalent toVrst(n+1). The reset and charge accumulation signals of the desiredpixel 650 and the reset and comparison signals of reference pixel 652stored in the sample and hold circuits columns n, n+1 are now availablefor the differential readout circuit to determine Vsig_diff(n). At adifferent time the reference pixel 652 is read out as the desired pixeland another neighboring pixel, either a pixel above, for pixel 650, forexample, or a pixel below, is used as the reference pixel. The steps toread out the reference pixel 652 as the desired pixel are similar tothose described above when pixel 650 is the desired pixel.

Turning to FIG. 9, a differential readout pixel circuit in accordancewith an another exemplary embodiment of the invention is depicted. TheFIG. 9 differential readout pixel circuit 80 differs from thedifferential readout pixel circuit 60 in FIG. 7 in that the pixels are3T pixels instead of 4T pixels. As known in the art, a 3T pixel omitsthe transfer gate between the photodiode and a sensing node. Thus, the3T pixel 850 has a photodiode 862, a reset gate 890, a source followertransistor 886, and a row select switch 888. The order of a readoperation from a 3T pixel is different than from a 4T pixel. Without atransfer control gate to isolate the charge accumulated signal from theNode A in the 3T pixel, the charge accumulated signal is first sampledfrom the Node A and then subsequently the reset signal is sampled fromthe Node A. Therefore, a pixel is used as a reference pixel after it hasbeen read out as a desired pixel (e.g., the photo integrated chargevoltage and the reset charge have been read out). Thus, the pixel in therow behind, e.g., row n−1, serves as a reference pixel. Due tononlinearity concerns, it is preferable to take a pixel from an alreadyread row—the row behind—as the reference pixel.

The operation of circuit of FIG. 9 is now described with reference tothe simplified signal timing diagram of FIG. 10. To read from desiredpixel 850 and the reference pixel 848, where pixel 848 has previouslybeen readout as a desired pixel and not subsequently been reset since ithas been readout, the row select lines 859, 860 are enabled bycorresponding row select pulses. The comparison signal voltages are thensampled by the sample and hold circuits connected to column lines 870,871. Thus, Vsig of the desired and reference pixel is stored. The resetline rst_n 890 of the desired pixel is pulsed after which it isdisabled. The reset voltages are then sampled by the sample and holdcircuits connected to column lines 870, 871. Thus, Vrst of the desiredand reference pixel are stored. Row select lines 859, 860 are thendisabled. The voltages stored in the sample and hold circuits for thetwo pixels are now available for the differential readout circuit todetermine the Vsig_diff(n). The remaining signals in the FIG. 10 timingdiagram describe the read out from pixel 852 as a desired pixel andpixel 850 as a reference pixel. In an alternative embodiment, the pixelin the row ahead is used as the reference pixel (e.g., pixel 852,instead of pixel 848, is the reference pixel to pixel 850).

The method and apparatus aspects of the invention are embodied in animage device 1140 shown in FIG. 11 which provides an image outputsignal. The image output signal can also be applied to a processorsystem 1100, also illustrated in FIG. 11. A processor based system, suchas a computer system, for example, generally comprises a centralprocessing unit (CPU) 1110, for example, a microprocessor, thatcommunicates with one or more input/output (I/O) 1150 over a bus 1170.The CPU 1110 also exchanges data with random access memory (RAM) 1160over bus 1170, typically through a memory controller. The processorsystem may also include peripheral devices such as a floppy disk drive1120 and a compact disk (CD) ROM drive 1130 which also communicate withCPU 1110 over the bus 1170. Imager device 1140 is coupled to theprocessor system and includes a pixel imaging circuit as described alongwith respect to FIGS. 5, 7, and 9.

Although the embodiments described utilize a desired and referencepixel, the invention is not so limited and the invention is alsoapplicable to CMOS pixel arrays in which more than one photodiode fromdifferent pixels are switchably coupled to a floating diffusion node.Turning to FIG. 12 which depicts a pixel array having M times N circuitswhere each circuit has a shared floating diffusion node A 1299, a resettransistor 1284, a source follower transistor 1286, a row selecttransistor 1288, transfer transistors 1281, 1282, and 1283, andphotodiodes 1261, 1262 and 1263. Circuit 1250 is similar in architectureto pixel 150 of FIG. 1, with a difference in that circuit 1250 hasseveral photodiodes 1261, 1262, and 1263 switchably coupled throughrespective transfer transistors 1281, 1282, and 1283 to floatingdiffusion node A 1299. Although FIG. 12 is shown with two rows of twocircuits each having three photo diodes, implementation of the array isnot so limited.

A read out operation of circuit 1250 is similar to the read outoperation of circuit 150 of FIG. 1 in that before the read out of thecharge accumulated signal from each respective photodiode 1261, 1262,and 1263, a reset operation is performed by a reset signal beingtemporarily applied to reset transistor 1284.

A differential readout may be applied to the pixel array 1210 using anembodiment of the present invention, where circuit 1250 serves as adesired circuit and circuit 1252 serves as the reference circuit. Forexample, using a readout operation similar to that described above withrespect to a differential readout of the pixels 450, 452 in FIG. 5, adifferential read out of circuits 1250, 1252 is done. For example, acharge accumulated signal from photodiode 1261 of circuit 1250 and areset signal from circuit 1250 is compared with a comparison signal anda reset signal from circuit 1252. Then a charge accumulated signal fromphotodiode 1262 of circuit 1250 and a reset signal from circuit 1250 iscompared with a comparison signal and a reset signal from circuit 1252.After which, a charge accumulated signal from photodiode 1263 of circuit1250 and a reset signal from circuit 1250 is compared with a comparisonsignal and a reset signal from circuit 1252. At a different time,circuit 1252 is the desired circuit and circuit 1250 serves as thereference circuit. Although the readout operation of FIG. 12 isdescribed as sequentially reading out the photodiodes 1261, 1262, and1263, the readout order can be altered. Furthermore, even though FIG. 12is described with respect to a differential readout operation using thenearest neighboring circuit in the same row as the reference circuit,the invention is not so limited. Although FIG. 12 is describes circuitssharing a floating diffusion node, the invention is not so limited. Forexample, a circuit may share a single electrical component, e.g., a rowselect gate, a reset gate, a transfer gate, a diffusion node, a drain, acontact, etc., or a circuit may share a combination of electricalcomponents.

While the invention has been described and illustrated with reference tospecific exemplary embodiments, it should be understood that manymodifications and substitutions can be made without departing from thespirit and scope of the invention. Although the embodiments discussedabove describe specific numbers of transistors, photodiodes, conductivelines, etc., the present invention is not so limited. Additionally,although the embodiments disclose two signals being sampled from thereference circuit, e.g., reset and comparison, a single reference valuecan be taken and as both the comparison and reset value. Accordingly,the invention is not to be considered as limited by the foregoingdescription but is only limited by the scope of the claims.

1-79. (canceled)
 80. A method of operating an imaging pixel array of animage sensor, said method comprising: sampling a reset and a chargeaccumulated signal from a desired pixel during a first time interval;sampling a reset and a comparison signal from a reference pixel duringsaid first time interval, wherein said reference pixel is a desiredpixel at a different time interval; and using said reset and comparisonsignals from said reference pixel to offset noise from said desiredpixel.
 81. The method of claim 80, wherein said reset signal from saiddesired pixel is sampled simultaneously with said reset signal of saidreference pixel.
 82. The method of claim 81, wherein said chargeaccumulated signal from said desired pixel is simultaneously sampledwith said comparison signal of said reference pixel
 83. The method ofclaim 80, wherein said reference pixel is in a different column fromsaid desired pixel.
 84. The method of claim 80, wherein said referencepixel is in the same row as said desired pixel.
 85. The method of claim80, wherein said reference pixel is the nearest neighbor of said desiredpixel.
 86. The method of claim 80, wherein said reference pixel is in adifferent row from said desired pixel.
 87. The method of claim 80,wherein said reference pixel is in the same column as said desiredpixel.
 88. The method of claim 80, wherein said reference pixel is thenearest neighbor of said desired pixel.
 89. The method of claim 84,wherein said sampling further comprises: enabling a reset voltage tocharge a respective Node A of said desired and reference pixel; samplingsaid Node A of said desired pixel and storing as said reset signal ofsaid desired pixel; sampling said Node A of said reference pixel andstoring as said reset signal of said reference pixel; enabling aphotodiode of said desired pixel to charge Node A of said desired pixel;sampling said Node A of said desired pixel and storing as said chargeaccumulated signal of said desired pixel; and sampling said Node A ofsaid reference pixel and storing as said comparison signal of saidreference pixel.
 90. The method of claim 87, wherein said samplingfurther comprises: enabling a reset voltage to charge a respective NodeA of said desired and reference pixel; sampling said Node A of saiddesired pixel and storing as said reset signal of said desired pixel;sampling said Node A of said reference pixel and storing as said resetsignal of said reference pixel; enabling a photodiode of said desiredpixel to charge Node A of said desired pixel; sampling said Node A ofsaid desired pixel and storing as said charge accumulated signal of saiddesired pixel; and sampling said Node A of said reference pixel andstoring as said comparison signal of said reference pixel.
 91. Themethod of claim 89, wherein said using further comprises: determining adifferential signal using said reset signal and charge accumulatedsignal of said desired pixel and said reset signal and comparison signalof said reference pixel.
 92. The method of claim 80, wherein said usingfurther comprises: determining a differential signal using said resetsignal and charge accumulated signal of said desired pixel and saidreset signal and comparison signal of said reference pixel.
 93. Themethod of claim 80, wherein said a desired circuit has a shared floatingdiffusion node and said reference circuit has a shared floatingdiffusion node.
 94. An image sensor, comprising: a desired pixel forgenerating a reset and charge accumulation signal during a first timeinterval; a reference pixel for generating a reset signal and comparisonsignal during said first time interval, wherein said reference pixel isa desired pixel at a different time interval; a circuit for sampling andholding said reset and charge accumulated signals generated by saiddesired pixel and said reset and comparison signals generated by saidreference pixel; and a combining circuit for generating an output basedon combination of said reset and charge accumulated signals generated bysaid desired pixel and said reset and comparison signals generated bysaid reference pixel.
 95. The sensor of claim 94, wherein said desiredpixel is in a same column of said reference pixel.
 96. The sensor ofclaim 94, wherein said desired pixel is the nearest neighbor of saidreference pixel.
 97. The sensor of claim 94, wherein said desired pixelis in a same row of said reference pixel.
 98. The sensor of claim 94,wherein said desired pixel is the nearest neighbor of said referencepixel.
 99. The system of claim 94, wherein said desired pixel is in therow below said reference pixel.